Tuesday, Oct. 14, 2008, 12 noon, ECSS 2.415
"Multi heterogeneous SIMPLE core SoC architecture for next generation multiple
The rapid growth in number and diversity of wireless standards is demanding a paradigm shift in architecture design for radio processing. Current DSP-based ASIC-bound computing models are less effective in terms of performance and power for several reasons, including the fact that instruction set architecture (ISA) of DSPs is inefficient compared to that of any specialized processor for radio computing.
The goal of our research project is to develop a novel programmable system-on-chip (SoC) architecture that will have heterogeneous hardware for instruction and function acceleration to meet the performance requirements of diverse wireless standards. The envisioned SoC will consist a layout of multiple programmable radio processor (PRP) cores, where each PRP core is designed as a Single Instruction Multiple Programmable eLEments (SIMPLE) processor. This design framework will facilitate a performance-effective yet flexible platform for radio processing. In this talk, I will first present an overview of our research outcomes in the past five years, and then elaborate on the current research project.
Lunch will be provided.